1. Field of the Invention
The invention relates in general to testing an integrated circuit and, in particular, to binning the performance of the integrated circuit.
2. Description of the Prior Art
Conventionally, function and AC scan patterns are used to test the functionalities and the performance of an integrated circuit. That is, functional and AC patterns are used to verify the correctness and operating speed of the chip, wherein a clocking speed is fed into the chip along with the patterns.
FIG. 1 illustrates a conventional flow of correlating actual speed of a chip with functional test patterns. In step 101, the chip is tapped out after all the design has been layout and verified. In step 102, after the chip is fabricated, post-silicon testing and data can be collected for further analyses. In step 103, the correlation between the performance of the chip and the functional/AC-Scan patterns can be determined. In step 104, performance binning using the above-mentioned correlation can be performed. However, it's costly and time consuming to correlate the actual speed with a large number of functional/AC patterns.
In another aspect of the conventional method, critical paths of a chip are observed to obtain the delay of the critical paths so as to determine the performance of the chip. However, thousands of paths may become candidates of critical paths in the post-silicon stage. A single ROSC (Ring Oscillator) or duplicated critical path is not effective to correlate so many critical paths varying in the post-silicon stage. Consequently, it is not an efficient way to correlate the actual speed with critical paths of a chip.
Therefore, what is needed is an effective and efficient way to determine the performance, or speed, of a chip.